Delay testing of PD-SOI circuits

Delay testing of SOI circuits: Challenges with the history effect

Testing Partially-Depleted Silicon-On-Insulator (PDSOI) integrated circuits presents new challenges that were not concerns in previous bulk CMOS technologies. Gates are affected by a variation in delay based on threshold voltage fluctuations. The fluctuations are dependent on the switching history of the device and this poses a serious challenge with regard to testing delays. To ensure worst-ca...

Testing domino circuits in SOI technology

The proliferation of both Partially Depleted SiliconOn-Insulator (PD-SOI) technology and domino circuit styles has allowed for increases in circuit performance beyond that of scaling traditional bulk CMOS static circuits. However, interactions between dynamic circuit styles and PD-SOI complicate testing. This paper describes the issues of testing domino circuits fabricated in SOI technology and...

Very Low Voltage Testing of SOI Integrated Circuits

Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the context of testing Silicon-On-Insulator (SOI) integrated circuits. In the VLV regime, the history effect, which describes how delays through SOI circuits vary based on a circuit’s recent switching history, is amplifie...

Statistical timing and leakage power analysis of PD-SOI digital circuits

This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIMSOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is impr...

Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits